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1/13 xc61h series voltage detector with delay circuit built-in v in resetb v ss 3 1 2 r pull resetb input v in v ss not necessary with cmos output products p xc61hn series general description the xc61h series is a highly accurate, low power consumption cmos voltage detector with a delay circuit. detect voltage is accurate with minimal temperature drift. output configurat ions are available in both cmos and n-channel open drain. since the full delay circuit is built-in, an external delay-time capacitor is not necessary so that high density mounting is po ssible. applications microprocessor reset circuitry system battery life and charge voltage monitors memory battery back-up circuits power-on reset circuits power failure detection delay circuitry typical performance characteristics features detect voltage accuracy : 2% low power consumption : 1.0 a(typ.)[ v in =2.0v ] detect voltage range : 1.6v ~ 6.0v (0.1v increments) operating voltage range : 0.7v ~ 10.0v detect voltage temperature characteristics : 100ppm/ (typ.) built-in release delay time : 1ms (min.) 50ms (min.) 80ms (min.) output configuration : n-ch open drain or cmos package : sot-23 environmentally friendly : eu rohs compliant, pb free typical application circuits ambient temperature: ta ( ) release delay time (t dr ) vs. ambient temperature etr0212-003a release delay time: t dr (ms) ?? rpull is not necessary with cmos output products
2/14 xc61h series top view designator item symbol description c cmos output output configuration n n-ch open drain output ? detect voltage (v df ) 16 ~ 60 e.g. 2.5v 2 , 5 1 50ms ~ 200ms 4 80ms ~ 400ms release delay time 5 1ms ~ 50ms detect accuracy 2 2.0% (*2) ? - (*1) package (oder unit) mr-g sot-23 (3000/reel) pin number sot-23 pin name function 1 v ss ground 2 resetb output 3 v in supply voltage input pin configuration product classification ordering information xc61h ?????? - (*1) block diagrams (1)cmos output pin assignment (2)n-ch open drain output (*1) the ?-g? suffix indicates that the products are hal ogen and antimony free as well as being fully rohs compliant. (*2) no parts are available with an accuracy of 1%
3/13 xc61h series parameter symbol ratings units input voltage v in 12.0 v output current i out 50 ma cmos v ss -0.3 ~v in +0.3 output voltage n-ch open drain restb v ss -0.3 ~ 12 v power dissipation sot-23 pd 250 mw operating temperat ure range topr -30 +80 storage temperature range tstg -40 +125 parameter symbol conditions min. typ. max. units circuit detect voltage v df v df(t) x 0.98 v df(t) v df(t) x 1.02 v hysteresis width v hys v df x 0.02 v df x 0.05 v df x 0.08 v v in = 1.5v - 0.9 2.6 v in = 2.0v - 1.0 3.0 v in = 3.0v - 1.3 3.4 v in = 4.0v - 1.6 3.8 supply current (*1) i ss v in = 5.0v - 2.0 4.2 a operating voltage v in v df =1.6v 6.0v 0.7 - 10.0 v v in = 1.0v 1.0 2.2 - v in = 2.0v 3.0 7.7 - n-ch, v ds = 0.5v v in = 3.0v 5.0 10.1 - v in = 4.0v 6.0 11.5 - v in = 5.0v 7.0 13.0 - output current i out p-ch, v ds =2.1v (cmos output) v in = 8.0v -10.0 -2.0 ma cmos output - 0.01 - leakage current nch open drain i leak v in =10.0v, v out =10.0v - 0.01 0.1 a detect voltage temperature characteristics v df topr ? v df - 100 - ppm/ - 50 - 200 80 - 400 release delay time (v dr reseb inversion) t dr v in changes from 0.6v to 10v 1 - 50 ms ta = 2 5 v df (t) is nominal detect voltage value release voltage: v dr = v df + v hys (*1) the supply current during power-start until ou tput being stable (during release operation) is 2 a greater with comparison to the period after the completion of release operation because of the shoot-through current in delay current. a bsolute maximum ratings ta = 2 5 electrical characteristics
4/14 xc61h series operational explanation cmos output an input voltage v in starts higher than the release voltage v dr . then, v in voltage will gradually fall. when v in voltage is higher than detect voltage v df , output voltage resetb is equal to the v in voltage. *note that high impedance exists at resetb with the n-cha nnel open drain configuration. if the resetb pin is pulled up, resetb will be equal to the pull up voltage. when v in falls below v df , resetb will be equal to ground voltage v ss level (detect state). * note that this also applies to n-channel open drain configurations. when vi n falls to a level below that of the minimum operating voltage v min, output will become unstable. *when the output pin is generally pulled up with n-channel open drain configurations, output will be equal to pull up voltage. when v in rises above the v ss level (excepting levels lower than minimum operating voltage), resetb will be equal to v ss until v in reaches the v dr level. although v in will rise to a level higher than v dr , resetb maintains ground volta ge level via the delay circuit. after taking a release delay time, v in voltage will be output at the resetb pin. *high impedance exists with the n-channel open drain c onfiguration and that voltage will be dependent on pull up. timing chart notes: 1. the difference between v dr and v df represents the hysteresis width. 2. release delay time ( t dr ) represents the time it takes until when v in voltage appears at resetb pin once the input voltage has exceeded the v dr level. release delay time (t dr ) output voltage (resetb)
5/13 xc61h series notes on use 1. please use this ic within the stated maximum ratings. t he ic is liable to malfunction should the ratings be exceeded. 2. when a resistor is connected between the v in pin and the input with cmos output configurations, irregular oscillation may occur as a result of voltage drops at r in if load current (i out ) exists. it is therefore re commend that no resistor be added. (refer to figure 1 below) 3. when a resistor is connected between the v in pin and the input with cmos output c onfigurations, irrespective of n-ch output configurations, oscillati on may occur as a result of shoot-through curr ent at the time of voltage release even if load current (i out ) does not exist. (refer to figure 1 below) 4. by connecting a resistor between the v in pin and the input, detect and release voltages will rise as a result of the ic's supply current flowing through the v in pin. 5. if a resistor (r in ) must be used, then please use with as small a level of input impedance as possible in order to control the occurrences of oscillation as described above. further, please ensure that r in is less than 10k and that c in is more than 0.1 f (figure 1). in such cases, detect and release voltages will rise due to voltage drops at r in brought about by the ic's supply current. 6. depending on circuit's operation, release delay time of th is ic can be widely changed due to upper limits or lower limits of operational ambient temperature. irregular oscillations (1) irregular oscillation as a result of output current with the cmos output configuration: when the voltage applied at in rises, release oper ations commence and the detecto r's output voltage increases. load current (i out ) will flow through r l . because a voltage drop (r in x i out ) is produced at the r in resistor, located between the input (in) and the v in pin, the load current will flow via the ic's v in pin. the voltage drop will also lead to a fall in the voltage level at the v in pin. when the v in pin voltage level falls below the detect voltage level, detect operations will commence. following det ect operations, load current flow will cease and since voltage drop at r in will disappear, the voltage level at the v in pin will rise and release operations will begin over again. irregular oscillation may occur with th is "release - detect - release" repetition. further, this condition will also appear via means of a similar mechanism during detect operations. (2) irregular oscillation as a re sult of shoot-through current: since the xc61h series are cmos ic s , shoot-through current will flow when the ic's internal circuit switching operates (during release and detect operat ions). consequently, irregular oscillation is liable to occur during release voltage operations as a result of output current which is influenced by this shoot-through current (figure 3). since hysteresis exists during detect operat ions, irregular oscillation is unlikely to occur. 1??r? fi g ure 1 use of in p ut resistor r in xc61hn series xc61hc series
6/14 xc61h series out v in resetb v ss ?h?` ?R out l ?hn` ss * ss * ????? ?h?` ?R v in resetb v ss notes on use irregular oscillations (continued) 2?k 3???k xc61hc series voltage drop figure 2 irregular oscillation by output current xc61hc series xc61hn series voltage drop (includes shoot-through current) figure 3 irregular oscillation by shoot-through current
7/13 xc61h series y y y y y v v v in v in v ss * r 220k resetb a v in v in v ss resetb a v in v in v ss v ds resetb a v in v in v ss v ds resetb v in v ss 220k measurement of waveform *r resetb test circuits *r is not necessary with cmos output products. circuit circuit circuit circuit circuit
8/14 xc61h series typical performance characteristics ??R , ?R v df, v dr (v) ?R v out (v) ?R v out (v) xc61hn1612 xc61hn1612 xc61hn1612 xc61hn1612 xc61hn2512 xc61hn2512 x c61hn2512 xc61hn2512 x c61hn1612 xc61hn3512 xc61hn3512 xc61hn3512 r-pull:100k ? ta = - 3 0 25 80 r-pull:100k ? ta = - 3 0 25 80 r-pull:100k ? ta = - 3 0 25 80 detect, release voltage: v df ,v dr (v) detect, release voltage: v df ,v dr (v) detect, release voltage: v df ,v dr (v) (3) detect voltage, release voltage vs. input voltage
9/13 xc61h series typical performance characteristics (continued) release delay time: t dr (ms) release delay time: t dr (ms) release delay time: t dr (ms) xc61hn1612 xc61hc2712 xc61hn2512 xc61hn2512 x c61hn3512 xc61hn3512 xc61hn 3 512 xc61hc 4412 xc61hc 3012 x c61hc3042 xc61hc3052 7 ambient temperature vs. release delay time (t dr )
10/14 xc61h series typical performance characteristics (continued) 8 input voltage vs. release delay time (t dr ) release delay time: t dr (ms) xc61hc2712
11/13 xc61h series packaging information sot-23
12/14 xc61h series mark products series 8 xc61h*******-g mark voltage (v) mark voltage (v) a 1. x p 1. x b 2. x r 2. x c 3. x s 3. x d 4. x t 4. x e 5. x u 5. x f 6. x v 6. x mark delay time 50ms 200ms delay time 80ms 400ms delay time 1ms 50ms detect voltage (v) xc61h***1***-g xc61h***4***-g xc61h***5***-g x.0 0 a n x.1 1 b p x.2 2 c r x.3 3 d s x.4 4 e t x.5 5 f u x.6 6 h v x.7 7 k x x.8 8 l y x.9 9 m z marking rule sot-23 represents decimal number of detect voltage and delay time. represents production lot number 0 to 9, a to z or inverted charac ters of 0 to 9, a to z repeated. (g, i, j, o, q,w excluded) *no character inversion used. represents product series standard represents output configuration and integer number of detect voltage cmos out p ut ( xc61hc series ) n-channel o p en drain ( xc61hn series )
13/13 xc61h series 1. the products and product specifications cont ained herein are subject to change without notice to improve performance characteristics. consult us, or our representatives before use, to confirm that the informat ion in this datasheet is up to date. 2. we assume no responsibility for any infri ngement of patents, pat ent rights, or other rights arising from the use of any information and circuitry in this datasheet. 3. please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. the products in this datasheet are not devel oped, designed, or approved for use with such equipment whose failure of malfuncti on can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. atomic energy; aerospace; transpor t; combustion and associated safety equipment thereof.) 5. please use the products listed in this datasheet within the specified ranges. should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. we assume no responsibility for damage or loss due to abnormal use. 7. all rights reserved. no part of this dat asheet may be copied or reproduced without the prior permission of torex semiconductor ltd.

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